1. Field of the Invention
The present invention generally relates to photomasks, and more particularly to a photomask used for forming microscopic patterns in manufacturing an electronic device such as a semiconductor device or a magnetic element. Furthermore, the present invention relates to a method of manufacturing an electronic device with the use of such a photomask.
2. Description of the Related Art
In recent years, requirements have been identified for forming extremely microscopic device patterns in manufacturing ultra-microscopic semiconductor integrated circuit devices and magnetic elements such as magnetic heads. Various technologies have been proposed for forming microscopic elements.
In order to form microscopic device patterns on a wafer by exposing the wafer to light, it is necessary to use short-wavelength light and an optical system with a high numerical aperture. However, an optical system with a high numerical aperture has a shallow focal depth. Therefore, if such an optical system is used for exposing a wafer to light to form a desired microscopic pattern on the wafer, it will be necessary to maintain precise focusing across the entire wafer surface. However, the wafer surface will inevitably have some undulations, and therefore it is difficult to maintain precise focusing across the entire wafer surface. This problem is particularly significant when exposing the wafer to form an isolated pattern.
In order to solve this problem, the following super-resolution technology is known. That is, so-called assist patterns are added onto a photomask carrying a desired device pattern, on either side of the device pattern. The assist patterns are not resolved on the wafer. By adding such assist patterns, the focus range can be expanded. This super-resolution technology makes it possible to expand the focus range, so that adverse effects of undulations on the wafer can be attenuated.
Patent Document 1: Japanese Laid-Open Patent Application No. 2000-206671
FIGS. 1A and 1B illustrate a positive type photomask 10A and a negative type photomask 10B, respectively, having assist patterns formed thereon.
Referring to FIG. 1A, on the photomask 11A, a primary pattern 11A corresponding to an exposing pattern to be formed on the wafer by exposure is formed as a light shielding pattern. A pair of assist patterns 12A is formed, one assist pattern 12A on either side of the primary pattern 11A, which assist patterns 12A are spaced apart from the primary pattern 11A. The width of each assist pattern 12A is such that the assist pattern 12A will not be resolved on the wafer. The assist patterns 12A are also formed as light shielding patterns.
On the negative type photomask 10B shown in FIG. 1B, a primary pattern 11B corresponding to an exposing pattern to be formed on the wafer by exposure is formed as a slit in an opaque film. A different pair of assist patterns 12B is formed, one assist pattern 12B on either side of the primary pattern 11B. The width of each assist pattern 12B is such that the assist pattern 12B will not be resolved on the wafer.
FIGS. 2A and 2B illustrate examples of photomasks having two assist patterns on either side of the primary pattern. FIG. 2A illustrates a positive type photomask 10C and FIG. 2B illustrates a negative type photomask 10D.
Referring to FIG. 2A, the photomask 10C has the primary pattern 11A that is a light shielding pattern. The pair of assist patterns 12A that are light shielding patterns are formed, one assist pattern 12A on either side of the primary pattern 11A. The width of each assist pattern 12A is such that the assist pattern 12A will not be resolved on the wafer. Furthermore, another pair of assist patterns 13A is formed outside of the assist patterns 12A. The width of each assist pattern 13A is such that the assist pattern 13A will not be resolved on the wafer.
The photomask 10D shown in FIG. 2B has the primary pattern 11B that is a slit pattern formed in an opaque film. The pair of assist patterns 12B that are slit patterns formed in the opaque film are formed, one assist pattern 12B on either side of the primary pattern 11B. The width of each assist pattern 12B is such that the assist pattern 12B will not be resolved on the wafer. Furthermore, another pair of assist patterns 13B is formed outside of the assist patterns 12B. The width of each assist pattern 13B is such that the assist pattern 13B will not be resolved on the wafer.
FIG. 3 is a flowchart of a procedure of adding such assist patterns to a primary pattern.
Referring to FIG. 3, in step S1, original pattern data of a photomask pattern is provided. In step S2, the lengths between patterns are measured from the pattern data.
In step S3, reference is made to insertion rules for inserting assist patterns, such as those described in Table 1. In step S4, assist patterns are inserted according to the insertion rules.
TABLE 1PatternNo. ofintervalsassistLocation for arrangingD (nm)patternsassist patterns660 ≦ D4First pair - 100 nm awayfrom primary (device) patternSecond pair - 100 nm awayfrom first pair520 ≦ D < 6603One pair - 100 nm away fromprimary (device) patternAt center between assistpatterns380 ≦ D < 5202100 nm away from primary(device) pattern240 ≦ D < 3801At center between primary(device) patternsD < 2400—
In step S5, the lengths between the patterns are measured once again. In step S6, a photomask pattern including assist patterns are output as an original pattern.
Referring to Table 1, if intervals between patterns on a wafer are greater than or equal to 660 nm, a total of four assist patterns will be inserted for each pattern. Specifically, a first pair of assist patterns will be inserted at locations 100 nm away from the primary pattern, and a second pair of assist patterns will be inserted at locations 100 nm away from the first pair of assist patterns. If intervals between patterns on a wafer are greater than or equal to 520 nm and less than 660 nm, a total of three assist patterns will be inserted for each pattern. A pair of assist patterns will be inserted at locations 100 nm away from the primary pattern, and a single assist pattern will be inserted at the center between two assist patterns. If intervals between patterns on a wafer are greater than or equal to 380 nm and less than 520 nm, a total of two assist patterns will be inserted at locations 100 nm away from the primary pattern on the wafer for each pattern. If intervals between patterns on a wafer are greater than or equal to 240 nm and less than 380 nm, one assist pattern will be inserted at the center between primary patterns. If intervals between patterns on a wafer are less than 240 nm, no assist patterns will be inserted. In Table 1, each numeral represents a length on a wafer in units of nm.
FIG. 4 illustrates relationships between focus positions and critical dimensions (CD) of patterns formed on a wafer by exposure. FIG. 4 illustrates three cases. In the first case, as shown in FIG. 5A, only a primary pattern 11A having an exposed width of 100 nm is provided on a wafer (which width is 400 nm on a mask), and no assist patterns are provided. In the second case, as shown in FIG. 5B, on either side of the primary pattern 11A shown in FIG. 5A, there is provided a pair of assist patterns 12A each having an exposed width of 40 nm on a wafer (which width is 160 nm on a mask) and at a location 100 nm away from the primary pattern 11A (400 nm away on a mask). In the third case, as shown in FIG. 5C, on either side of the assist patterns 12A shown in FIG. 5B, there is further provided one of a pair of assist patterns 13A, each assist pattern 13A having an exposed width of 40 nm on a wafer (which width is 160 nm on a mask) and at a location 100 nm away from the inner assist patterns 12A (400 nm away on a mask). In FIG. 4, the zero position of the horizontal axis corresponds to a just focus position. The relationships shown in FIG. 4 are obtained in a simulation according to conditions shown in Table 2.
TABLE 2Wavelength193nmNumerical aperture (NA)0.85σOutside = 0.85Inside = 0.425Focus step0.01μmCD target100nm
Referring to FIG. 4, in a case where the tolerance of the critical dimension is 10% of the target line width (i.e., 90 nm), and the focusing is shifted from the just focus position by about 0.09 μm, the critical dimension will exceed the tolerance if no assist patterns are provided; however, if a pair of assist patterns are provided, the critical dimension will not exceed the tolerance even when the focusing is shifted by about 0.14 μm; furthermore, if two pairs of assist patterns are provided, the focusing range will be greater than or equal to 0.20 μm.
As described above, the assist pattern technology is indispensable in manufacturing today's ultra-microscopic semiconductor devices having a gate length of less than 0.1 μm. However, there has been a critical problem in conventional mask inspection processes.
FIGS. 6A and 6B illustrate a conventional mask inspection process.
As shown in FIGS. 6A and 6B, this mask inspection process is applicable to a case where the chips A of the same type are arranged adjacent to each other on a photomask. A photomask 203, which corresponds to any of the photomasks described above, is placed on an X-Y stage 202 of an inspection device. Under the control of a control device 211, a horizontal alignment 209 and an illumination optical system 201 are adjusted. Subsequently, the inspection starts.
When the inspection starts, as shown in FIG. 6B, the X-Y stage 202 is moved by the control device 211 via a driving unit 210 in such a manner that the inspection area is scanned from one end to the other end. Light that has passed through the photomask is condensed onto a light receiving element 205 by an objective lens 204, and corresponding image data are saved in an image memory 206.
When a scanning operation of one chip ends, the scanning operation for the next chip starts. At this stage, in a defect detection circuit 207, image data acquired by the light receiving element 205 are compared with image data at a corresponding portion of a previous chip saved in the image memory 206. When a difference is detected, the corresponding coordinates are saved as a defect in a defect information memory 208.
When such a scanning operation ends, the contents in the image memory 206 are cleared, and the next scanning operation starts.
When such a scanning operation ends, patterns near the coordinates that have been saved are displayed on a defect confirmation screen. The operator confirms, by visual inspection, whether the detected defect is actually a defect, and determines whether a correction is to be made.
A similar inspection can be performed by using design data as the standard data, instead of using image data of a previous chip.
FIGS. 7A and 7B illustrate photomasks including such defects. FIG. 7A illustrates a case where there is a defect 11X in the primary pattern 11A, while FIG. 7B illustrates a case where there is a defect 12X in the assist pattern 12A. Although not illustrated, similar defects may occur in a photomask having two or more pairs of assist patterns or in a negative type photomask.
As described above, in order to inspect such photomasks, the operator (a human being) needs to confirm the defect by visual inspection at the final stage. Considering that a photomask carries many patterns, the workload of the operator for making such inspections is high, and therefore, it is necessary to reduce this workload.